The Aplio/TRIO is an integrated processor designed for Smart Internet Appliances such as Internet telephony (VoIP) appliances. The Aplio/TRIO provides the connection to the Internet (internal modem) while at the same time providing real time voice compression and echo cancellation. Alternatively, it can provide two channels of voice compression and no modem.

Features
Description
Bloc Diagrams
Aplio/TRIO Block Diagram
DSP Subsystem Block Diagram
Application Example: Standalone Internet Telephone
Functional Description
ARM7TDMI Core
DSP Subsystem
Boot ROM
Boot Code Operation
EBI: External Bus Interface
AIC: Advanced Interrupt Controller
PIO: Parallel I/O Controller
USART
Serial Peripheral Interface
Timer Counter
Watchdog Timer
Special Functions
Packaging
Size
Power Consumption



Features Back to top

ARM7TDMITM ARM(R) Thumb(R) Processor Core

Two 16-bit Fixed-point OakDSPCoreTM Cores

256 x 32-bit Boot ROM  

88K bytes of Integrated Fast RAM for Each DSP  

Flexible External Bus Interface with Programmable Chip Select

Dual Codec Interface  

Multi-level Priority, Individually Maskable, Vectored Interrupt Controller  

Three 16-bit Timers/Counters  

Additional Watchdog Timer  

Two USARTs with FIFO and Modem Control Lines  

Industry Standard Serial Peripheral Interface (SPI)  

Up to 23 General-purpose I/O Pins  

On-chip DRAM Controller  

JTAG Debug Interface  

Software Development Suites Available for ARM7TDMI and OakDSPCore  

Supported by a Wide Range of Ready-to-use Application Software, including Multitasking Operating System, Networking, Modem, and Voice Processing Functions  

Available in 160-lead PQFP or 240-lead PQFP Package

3.3V Power Supply  

Description Back to top
The Aplio/TRIO is a high-performance processor, specilly designed for Internet Appliance applications, such as Internet telephony (Voice over Internet Protocol - VoIP). The Aplio/TRIO is built around an ARM7TDMI microcontroller core running at 20 MHz, with 2 DSP co-processors running at 40 MHz each, all three processors delivering unmatched performance for low power consumption.
In a typical standalone VoIP phone, one DSP handles the voice processing functions (voice compression, acoustic echo cancellation, etc.), while the other one deals with the telephony functions (dialing, line echo cancelation, callerID detection, high speed modem, etc.). In such an application, the power of the ARM7TDMI allows it to run the VoIP protocol stacks as well as all the system control tasks.

Aplio provides the Aplio/TRIO with 5 layers of software bricks, making it a complete, proven and scalable solution.

The 5 layers are:

  Operating System
         Special port of the Linux kernel
  DSP Softwares
         Comprehensive set of tunable DSP algorithms for modems and voice processing specially tailored to be run by the DSP Subsystem
  Libraries
         Extensive set of standards supported
  Session Layer
         Including PacketPlusTM Technology delivering True Telephone Sound Quality
  Applications
         Broad range of Killer applications like VoIP, E-mail, Light Browsing and more.

For a complete presentation of the Software Modules, click here.

Application Example: Standalone Internet Telephone Back to top

Functional Description
ARM7TDMI Core Back to top

The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor architecture is Von Neumann load/store architecture, which is characterized by a single data and address bus for instructions and data. The CPU has two instruction sets, the ARM and the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and provides maximum performance. Thumb  instructions are 16-bit wide and give maximum code density. Instructions operate on 8-, 16- and 32-bit data types.
The CPU has seven operating modes. Each operating mode has dedicated banked registers for fast exception handling. The processor has a total of 37 32-bit registers, including 6 status registers.

Features Benefits
  • 32-bit RISC
  • 20 MHz
   High Processing Power
  Small die size   Low cost
  Commonly used under the ucLinux
  Operating System for the main application
  • Royalty-Free
  • Shorter Porting times
    		•

    DSP Subsystem Back to top

    The Aplio/TRIO has two identical DSP subsystems.
    Each DSP subsystem is composed of:

    • an OakDSPCore running at 40 MHz
    • 2K x 16 of X-RAM
    • 2K x 16 of Y-RAM
    • 16K x 16 of general purpose data RAM
    • 24K x 16 of loadable program RAM
    • one 256 x 16 dual-port mailbox
    • one codec interface
    The DSP subsystem is fully autonomous. The local X- and Y-RAM allows it to reach its maximum processing rate, and a local large data RAM enables complex DSP algorithms to be implemented. The large size of the loadable program RAM permits the use of functions as complex as a V34 modem or a low bit-rate vocoder.
    During boot time, the ARM7TDMI core as the ability to maintain the OakDSPCore in reset state and to upload DSP boot code. When the OakDSPCore reverts to an active state this boot code can be used to get the complete DSP application code from the ARM7TDMI through the mailbox.
    When the OakDSPCore is running the dual port mailbox is used as the communication channel between the ARM7TDMI and the OakDSPCore.
    One programmable codec interface is directly connected to each OakDSPCore. It allows the connection of most industrial voice, multimedia or data codecs.

    Features Benefits
     Two 16-bit fixed-point DSP cores  Empowers 2 simultaneous audio signal processing streams
     2*40 MHz  High Processing Power
     Designed for large computation-intensive tasks (like modem, codec, voice recognition)  Perfect for Internet access and simultaneous Value Added voice applications

    Boot ROM Back to top
    The ARM7TDMI has the ability to boot either from an external memory or from the on-chip 256 x 32-bit boot ROM.

    Boot Code Operation Back to top
    The internal boot sequence allows programming of the ARM7TDMI program RAM through a serial port. When the download is complete, a branch is executed to the downloaded code.

    EBI: External Bus Interface Back to top
    The EBI generates the signals which control access to external memory or memory-mapped peripherals. The EBI is fully programmable and can address up to 64M bytes. The interface to external devices is composed of common address and data buses, and separate control lines to allow the connection of static or dynamic devices.
    The main features are:
    • External memory mapping
    • Up to two chip select lines
    • 8- or 16-bit data bus
    • Byte write or byte select lines
    • Remap of boot memory
    • Support for both static and dynamic memories
    • Two different read protocols for static memories
    • Support for early read/early write for dynamic memories
    • Programmable wait state generation
    • Programmable data float time.
    AIC: Advanced Interrupt Controller Back to top
    The Aplio/TRIO has an 8-level priority interrupt controller. The interrupt controller outputs are connected to the NFIQ (fast interrupt request) and the NIRQ (normal interrupt request) of the ARM7TDMI core. The processor's NFIQ can only be asserted by the external fast interrupt request input (FIQ). The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals or by the external interrupt request line IRQ0.
    An 8-level priority encoder allows the application to define the priority between the different interrupt sources. Interrupt sources are programmed to be level-sensitive or edge-sensitive. External sources can be programmed to be positive or negative edge triggered, or low- or high-level sensitive.

    PIO: Parallel I/O Controller Back to top
    The Aplio/TRIO has 23 programmable I/O lines. They can all be programmed as inputs or outputs. To optimize the use of available package pins, most of them are multiplexed with external signals of on-chip peripherals.
    The PIO lines are controlled by two separate and identical PIO controllers called PIOA and PIOB.
    The PIO controllers enable the generation of an interrupt on input change and insertion of a simple glitch filter on each PIO line.
    Some I/O lines have enough drive capability to power a LED.

    USART: Universal Synchronous/Asynchronous Receiver/Transmitter Back to top
    The Aplio/TRIO provides two identical full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller.
    The main features are:
    • Programmable Baud Rate Generator
    • Parity, Framing and Overrun Error Detection
    • Line Break Generation and Detection
    • Automatic Echo, Local Loopback and Remote Loopback
    • Multi-drop Mode : Address Detection and Generation
    • Interrupt Generation
    • Dedicated Peripheral Data Controller Channels
    • 6-, 7-, 8-, 9-bit character lenght
    Addionally to the Tx and Rx signals, the USART A provides several modem control lines.
    SPI: Serial Peripheral Interface Back to top
    The Aplio/TRIO includes an SPI which provides communication with external devices in master or slave mode.
    The SPI has four external chip selects which can be connected to up to 15 devices. The data length is programmable from 8- to 16-bit. It also allows communication with external processors or serial FLASH.

    Serial Peripheral Interface Pinouts
     Pin  Description  Mode  Function
     MISO  Master In
     Slave Out    		  Master
     Slave    		  Serial data input to SPI
     Serial data output from SPI
     MOSI  Master Out
     Slave In    		  Master
     Slave    		  Serial data output from SPI
     Serial data input to SPI
     SPCK Serial Clock  Master
     Slave    		  Clock output from SPI
     Clock input to SPI
     NPCSS  Periperal Chip Select / Slave Select  Master
     Master
     Slave    		  Output: Select peripheral
     Input: Low causes mode fault
     Chip Select for SPI
     NPCS(3.1)  Peripheral Chip Selects  Master  Extra Selects

    Timer Counter Back to top
    The Aplio/TRIO features three identical 16-bit timer/counters. They can be independently programmed to perform a wide range of functions, including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
    The triple timer/counter block has three external clock inputs, five internal clock inputs and two multi-purpose signals which can be configured by the user. Each timer drives an internal interrupt signal which can be programmed to generate processor interrupts via the Advanced Interrupt Controller.

    Features Benefits
     3 identical 16-bit counter channels  Independent for all application needs
     General purpose with Capture/Count/Waveform  All uses of General Purpose timers

    Watchdog Timer Back to top
    The Aplio/TRIO has an internal Watchdog Timer which can be used to prevent system lock-up if the software becomes trapped in a deadlock.

    Special Functions Back to top
               The Aplio/TRIO provides registers which implement the following special functions:

                    Chip identification
                    Reset status

    Packaging Back to top
    The Aplio/TRIO 1000 is supplied in a PQFP160 package. This provides the best compromise between external connectivity and cost.
    An alternative PQFP240 is also available, the Aplio/TRIO 1100. In addition to a larger I/O capability, it provides the application developer with the possibility of using advanced development tools for the DSP subsystem software.
    Althought this PQFP240 is more dedicated to development, it can also be used in production for systems which require a high level of connectivity: it offers up to 48 general purpose I/Os and a full width system bus (24 address bits and 32 data bits).

    Size Back to top
        160 pins : 28 x 28 mm2, pitch 0.65 mm
        240 pins : 32 x 32 mm2, pitch 0.5 mm

    Power Consumption Back to top
        In low power mode : < 100mw
        In normal power mode : Approx. 1 Watt
        Exact power consumption will depend on software activity


    Go to the Home Page

    To request more information, click here.
    To order a product, click here.

    Back to Top

    Copyright© 1997 to 2000 Aplio, Inc
    Unauthorized reproduction prohibited